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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? generates clocks for oc-3, stm-1, ds3, e3, ds2, ds1, e1, 19.44 mhz and st-bus ? meets jitter generation requirements for stm-1, oc-3, ds3, e3, j2 (ds2), e1 and ds1 interfaces ? compatible with gr-2 53-core sonet stratum 3 and g.813 sec timing compliant clocks ? provides ?hit-less? reference switching ? detects frequency of both reference clocks and synchronizes to any combin ation of 8 khz, 1.544 mhz, 2.048 mhz and 19.44 mhz reference frequencies ? continuously monitors both references for frequency accuracy exceeding 12 ppm ? holdover accuracy of 70x10 -12 meets gr-1244 stratum 3e and itu-t g.812 requirements ? meets requirements of g.813 option 1 for sdh equipment clocks (sec ) and gr-1244 for stratum 4e and stratum 4 clocks ? 3.3v power supply applications ? line card synchronization for sdh, sonet, ds3, e3, j2 (ds2), e1 and ds1 interfaces ? timing card synchronization for sdh and pdh network elements ? clock generation for st-bus and gci timing description the ZL30410 is a multi-service line card phase-locked loop designed to generate multiple clocks for sonet, sdh and pdh equipment including timing for st-bus and gci interfaces. the ZL30410 operates in normal (locked), holdover and free-run modes to ensure that in the presence of jitter and interruptions to the reference signals, the generated cl ocks meet international standards. the filtering char acteristics of the pll are hardware pin selectable and they do not require any external adjustable components. the ZL30410 uses an external 20 mhz master clock oscillator to provide a stable timing source for the holdover operation. november 2003 ordering information ZL30410qcc 80 pin lqfp -40 c to 85 c figure 1 - functional block diagram zarlink semiconductor us patent no. 5,602,884, uk patent no. 0772912, france brevete s.g.d.g. 077291 2; germany dbp no. 69502724.7-08 control state machine mux primary acquisition pll ms1 ms2 reset sec trst c19o c34/c44 c16o c8o c4o c2o c1.5o f16o f8o pri c6o holdover lock prior c155p/n e3ds3/oc3 f0o secondary acquisition pll refalign e3/ds3 jtag ieee 1149.1a master clock frequency calibration apll secor tms tdo tdi tc l k clock synthesizer core pll refsel fcs c20i vdd gnd oe 07 ZL30410 multi-service line card pll data sheet
ZL30410 data sheet table of contents 2 zarlink semiconductor inc. 1.0 ZL30410 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 acquisition plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 core pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 digitally controlled oscillator (dco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 lock indicator (lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.4 reference alignment (refalign). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 output clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 control state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 ZL30410 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.3 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 status pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 ZL30410 switching between clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 system start-up sequence: free-run --> holdover --> normal . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 single reference operation: normal --> auto ho ldover --> normal . . . . . . . . . . . . . . . . 17 4.1.3 single 8 khz reference operation: normal --> auto holdover--> holdover --> normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.4 dual reference operation: normal --> au to holdover--> holdover --> normal. . . . . 19 4.1.5 reference switching (refsel): normal --> holdover --> normal . . . . . . . . . . . . . . . . . . . . 20 4.2 power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ZL30410 data sheet 3 zarlink semiconductor inc. 1.0 ZL30410 pinout 1.1 pin connections figure 2 - pin connections for 80-pin lqfp package ZL30410 40 42 44 46 48 50 52 54 56 58 60 22 24 26 28 30 34 36 38 32 62 80 78 76 74 72 68 66 64 70 20 18 16 14 12 10 8 6 4 2 tdi tc l k tms tdo nc gnd pri sec e3/ds3 e3ds3/oc3 c155p c155n vdd avdd gnd ic gnd nc trst nc ms1 nc c4o c8o c16o f16o gnd vdd fcs nc f0o c2o ic nc nc ms2 gnd nc f8o secor oe nc reset nc ic ic ic gnd ic ic nc ic vdd ic ic ic ic nc c1.5o c19o refsel refalign vdd nc c20i c34/c44 gnd vdd holdover nc lock nc ic prior gnd ic c6o ic nc ic
ZL30410 data sheet 4 zarlink semiconductor inc. . pin description pin # name description 1ic internal connection . leave unconnected. 2-5 nc no internal bonding connection. leave unconnected. 6gnd ground . negative power supply. 7, 8 nc no internal bonding connection. leave unconnected. 9fcs filter characteristic select (input). in hardware co ntrol, fcs selects the filtering characteristics of the ZL30410. se t this pin high to have a loop filter corner frequency of 6 hz and limit the phase slope to 41 ns per 1.326 ms. set this pin low to have corner frequency of 12 hz with no phase slope limiting imposed. this pin is internally pulled down to gnd. 10 vdd positive po wer supply. 11 gnd ground . 12 f16o frame pulse st-bus 8.192 mb/s (cmos tristate output). this is an 8 khz, 61ns wide, active low framing pulse, which marks beginning of a st-bus frame. this frame pulse is typically used for st-bus operation at 8.192 mb/s. 13 c16o clock 16.384 mhz (cmos tristate output). this clock is used for st-bus operation at 8.192 mb/s. 14 c8o clock 8.192 mhz (cmos tristate output). this clock is used for st-bus operation at 8.192 mb/s. 15 c4o clock 4.096 mhz (cmos tristate output). this clock is used for st-bus operation at 2.048 mb/s. 16 c2o clock 2.048 mhz (cmos tristate output). this clock is used for st-bus operation at 2.048 mb/s. 17 f0o frame pulse st-bus 2.048 mb/s (cmos tristate output). this is an 8 khz, 244ns, active low framing pulse, which marks the beginning of a st-bus frame. this is typically used for st-bus operation at 2.048 mb/s and 4.096 mb/s. 18 ms1 mode select 1 (input). the ms1 and ms2 pins select the ZL30410 mode of operation (normal, holdover or free-run), see table 1 on page 14 for details. the logic level at this input is sampl ed by the rising edge of the f8o frame pulse. 19 ms2 mode select 2 (input). the ms2 and ms1 pins select the ZL30410 mode of operation (normal, holdover or free-run), see table 1 on page 14 for details. the logic level at this input is sampl ed by the rising edge of the f8o frame pulse. 20 f8o frame pulse st-bus/gci 8.192 mb/s (cmos tristate output). this is an 8 khz, 122 ns, active high framing pulse, which marks the beginning of a st-bus/gci frame. this is typically used for st-bus/gci operation at 8.192 mb/s. see figure 15 for details.
ZL30410 data sheet 5 zarlink semiconductor inc. 21 e3ds3/oc3 e3ds3 or oc3 selection (input). in hardwa re control, a logic low on this pin enables the c155p/n outputs (pin 30 and pin 31) and sets the c34/c44 output (pin 53) to provide c8 or c11 clocks. log ic high at this i nput disables the c155 clock outputs (high impedance) and sets c34/c44 output to provide c34 and c44 clocks. 22 e3/ds3 e3 or ds3 selection (input). in hardware control, when the e3ds3/oc3 pin is set high, logic low on e3/ds3 pin selects a 44.736 mhz clock on c34/c44 output and logic high selects 34.368 mhz clock. when e3ds3/oc3 pin is set low, logic low on e3/ds3 pin selects 11.184 mhz clock on c34/c44 output and logic high selects 8.592 mhz clock. 23 sec secondary reference (input). this input is used as a secondary reference source for synchronization . the ZL30410 can synchronize to the falling edge of the 8 khz, 1.544 mhz or 2.048 mhz clocks and the rising edge of the 19.44 mhz clock. in hardware control, selection of the input reference is based upon the refsel control input. this pin is internally pulled up to vdd. 24 pri primary reference (input). this input is used as a primary reference source for synchronization. the ZL30410 can synchronize to the falling edge of the 8 khz, 1.544 mhz or 2.048 mhz clocks a nd the rising edge of the 19.44 mhz clock. in hardware control, selection of the input reference is based upon the refsel control input. this pin is internally pulled up to vdd. 25 gnd ground . 26 ic internal connection . leave unconnected. 27 gnd ground . 28 avdd positive analog power supply . connect this pin to vdd. 29 vdd positive po wer supply . 30 31 c155n c155p clock 155.52mhz (lvds output). differential outputs for the 155.52 mhz clock. these outputs are enabled by applying logic low to e3ds3/oc3 input or they can be disabled by applying logic high. in the disabled state the lvds outputs are internally terminated with an integrated 100 ? resistor (two 50 ? resistors connected in series). the middle point of these resistors is internally biased from a 1.25v lvds bias source. 32 gnd ground . 33 nc no internal bonding connection. leave unconnected. 34 tdo ieee1149.1a test data output (cmos output). jtag serial data is output on this pin on the falling edge of tclk clock. if not used, this pin should be left unconnected. 35 tms ieee1149.1a test mode selection (3.3 v input). jtag signal that controls the state transition on the tap controller. this pin is internally pulled up to vdd. if not used, this pin should be left unconnected. pin description (continued) pin # name description
ZL30410 data sheet 6 zarlink semiconductor inc. 36 tclk ieee1149.1a test clock signal (5 v tolerant input). input clock for the jtag test logic. if not used, this pin should be pulled up to vdd. 37 trst ieee1149.1a reset signal (3.3 v input). asynchr onous reset for the jtag tap controller. this pin should be pulsed low on power-up to ensure that the device is in the normal functional state. this pin is internally pulled up to vdd. if this pin is not used then it should be co nnected to gnd. 38 tdi ieee1149.1a test data input (3.3 v input). input for jtag serial test instructions and data. this pin is internally pulled up to vdd. if not used, this pin should be left unconnected. 39 nc no internal bonding connection. leave unconnected. 40 nc no internal bonding connection. leave unconnected. 41 prior primary reference out of range (output). logic high at this pin indicates that the primary reference is off the pll centre frequency by more than 12ppm. see prior pin description in section 3.2 on page 15 for details. 42 c1.5o clock 1.544 mhz (cmos tristate output). this output provides a 1.544 mhz ds1 rate clock. 43 c6o clock 6.312 mhz (cmos tristate output). this output provides a 6.312 mhz ds2 rate clock. 44 ic internal connection . connect this pin to ground. 45 gnd ground . 46 c19o clock 19.44 mhz (cmos tristate output). this output provides a 19.44 mhz clock. 47 refsel reference source select (input). a logic low se lects the pri (primary) reference source as the input reference signal and logic high selects the sec (secondary) input. the logic level at this input is sampled at the rising edge of f8o. this pin is internally pulled down to gnd. 48 refalign reference alignment (input). in hardware control pulling this pin low for 250 s initiates phase realignment between the input reference and the generated output clocks. see section 2 .2.4 on page 9 for details. this pin should never be tied low permanently. internally this pin is pulled down to gnd. 49 vdd positive po wer supply . 50 nc no internal bonding connection. leave unconnected. 51 c20i clock 20 mhz (5 v tolerant input). this pin is the input for the 20mhz master clock oscillator. the clo ck oscillator should be connected directly (not ac coupled) to the c20i input and it must supply clock with duty cycle that is not worse than 40/60%. 52 gnd digital ground . pin description (continued) pin # name description
ZL30410 data sheet 7 zarlink semiconductor inc. 53 c34/c44 clock 34.368 mhz / clock 44.736 mhz (cmos output). this clock is programmable to be either 34.368 mhz (for e3 applications) or 44.736 mhz (for ds3 applications) when e3ds3/oc3 is high, or to be either 8.592 mhz or 11.184 mhz when e3ds3/oc3 is low. see description of e3ds3/oc3 and e3/ds3 inputs for details. 54 vdd positive po wer supply . 55 holdover holdover indicator (cmos output). logic high at this output indicates that the device is in holdover mode. 56 nc no internal bonding connection. leave unconnected. 57 lock lock indicator (cmos output). logic high at this output indicates that ZL30410 is locked to the input reference. see lock indicator description in section 2.2.3, ?lock indica tor (lock),? on page 9. 58 nc no internal bonding connection. leave unconnected. 59 ic internal connection . connect to logic high. 60 ic internal connection . connect to ground. 61 secor secondary reference out of range (output). logic high at this pin indicates that the secondary reference is off th e pll centre frequency by more than 12ppm. see secor (prior) pin description in section 3.2 on page 15 for details. 62 oe output enable (input). logic high on this input enables c19, f16 , c16 , c8, c6, c4 , c2, c1.5, f8 and f0 signals. pulling this input low will force the output clocks pins into a high impedance state. 63 nc no internal bonding connection. leave unconnected. 64 reset reset (5v tolerant input). the ZL30410 must be reset after power-up in order to set internal functional blocks into a default stat e. the internal reset is performed by forcing reset pin low for a minimum of 1 s after the c20 master clock is applied to pin c20i. this operation forces the ZL30410 internal state machine into a reset state for a duration of 625 s. 65 nc no internal bonding connection. leave unconnected. 66-69 ic internal connection. connect these pins to logic high. 70 gnd ground . 71, 72 ic internal connection (input). connect these pins to ground. 73 vdd positive po wer supply . 74 - 77 ic internal connection. connect these pins to logic high. 78, 79 nc no internal bonding connection. leave unconnected. 80 ic internal connection (input). connect this pin to ground. pin description (continued) pin # name description
ZL30410 data sheet 8 zarlink semiconductor inc. 2.0 functional description the ZL30410 is designed to provide timing for sdh and sonet equipment conforming to itu-t, ansi, etsi and telcordia recommendations. in addition, it generates clocks for sdh and pd h equipment operating at ds1, ds2, ds3, e1, and e3 rates. the ZL30410 provides clocks for industry standard st-bus and gci backplanes, and it also supports h.110 timing requirements. the functional block diagram of the ZL30410 is shown in figure 1 "functional block diagram" and its operation is described in the following sections. 2.1 acquisition plls the ZL30410 has two acquisition plls for monitoring avai lability and quality of the primary (pri) and secondary (sec) reference clocks. each acquisitio n pll operates inde pendently and locks to the fa lling edges of one of the three input reference frequencies: 8 khz, 1.544 mhz, 2.048 mhz or to the risi ng edge of 19.44 mhz. the reference frequency is automatically detected by the ZL30410 device. the primary and secondary acquisition plls are designed to provide indication of two levels of reference clock quality. for clarity, only the primary acquisition pll is re ferenced in the text, but the same applies to the secondary acquisition pll: - reference frequency drifts more than 12 ppm. in response, the prior (pri mary reference out of range) pin changes state to high, in conformance with stratum 3 requirements defined in gr-1244-core - reference frequency drifts more than 30000 ppm or that the reference has been lost completely. in response, the primary acquisition pll enters its own holdover mode which forces the core pll into the auto holdover state. outputs of both acquisition plls are connected to a multiplexer (mux), which allows selection of the desired reference. this multiplexer ch annels binary words to the core pll digital phase detector (instead of analog signals) which eliminates quantization errors and improves phas e alignment accuracy. the bandwidth of the acquisition pll is much wider than the bandwidth of the following core pll. this feature allows cascading acquisition and core plls without altering the transfer function of the core pll. 2.2 core pll the most critical element of the ZL30410 is its core pll, which generates a phase-locked clock, filters jitter and suppresses input phase transients. all of these feat ures are in agreement with international standards: - g.813 option 1 clocks for sdh equipment - gr-1244 for stratum 4e and 4 clocks when locked to a g.813 option 1 and 2 or sonet stratum 3 quality clock th e ZL30410 generate s clocks that also meet sonet stratum 3 or g.813 option 1 and 2 requirements. the core pll supports three mandatory modes of operat ion: free-run, normal (locked) and holdover. each of these modes places specific requirements on the buildin g blocks of the core pll. - in free-run mode, the core pll derives its output clock from the 20 mhz master clock oscillator connected to pin c 20i. the stability of the generated clocks re mains the same as th e stability of the master clock oscillator. - in normal mode, the core pll locks to one of the acquisition plls. both acquisition plls provide preprocessed phase data to the core pll including detection of reference clock quality. - in holdover mode, the core pll generates a clock ba sed on data collected from past reference signals. the core pll enters holdover mode if the attached acquisition pll switches into the holdover state or under external control. some of the key elements of the core pll are shown in figure 3 "core pll functional block diagram".
ZL30410 data sheet 9 zarlink semiconductor inc. figure 3 - core pll functional block diagram 2.2.1 digitally controlled oscillator (dco) the dco is an arithmetic unit that continuously generates a stream of numbers that represent the phase-locked clock. these numbers are passed to the clock synthesi zer (see section 2.3) where they are converted into electrical clock signals of various frequencies. 2.2.2 filters in normal mode, the clock generated by the dco is phase-locked to the input reference signal and band-limited to meet synchronization standards. the ZL30410 provides two hardware selectable (fcs pin) filtering options. the filtering characteristics are similar to a first order low pass filter with corner frequencies that support international standards: - 6 hz filter: supports g. 813 option 1 clock - 12 hz filter: supports line card applications for g.812, g.813, gr-1244 and gr-253 2.2.3 lock indicator (lock) the ZL30410 is considered locked (lock pin high) when the residual phase movement after declaring locked condition does not exceed 20 ns; as required by standard wander generation mtie and tdev tests. to ensure the integrity of the lock status indication, the ZL30410 holds lock pin low for a minimum of one second before declaring lock. the ZL30410?s locking process allows it to lock within the specified locking times to references with a fractional frequency offset of up to 20 ppm. 2.2.4 reference alignment (refalign ) when the ZL30410 finishes locking to a reference an arbitrary phase difference will remain between its output clocks and its reference; this phase difference is part of the normal operation of the ZL30410. if so desired, the output clocks can be brought into phase alignmen t with the pll reference by using the refalign control pin. fsm dco filters phase detector mux lock refalign fcs holdover
ZL30410 data sheet 10 zarlink semiconductor inc. using refalign with 1.544 mhz, 2.048 mhz or 19.44 mhz reference if the ZL30410 is lock ed to a 1.544 mhz, 2.04 8 mhz or 19.44 mhz reference, then the output clocks can be brought into phase alignment with the pll reference by using the refalign control pin according to the following procedure: - wait until the ZL30410 lock indication is high, indicating that it is locked - pull refalign low - hold refalign low for 250 s - pull refalign high after initiating a reference realignment the pll will enter holdover mode for 200ns while aligning the internal clocks to remove static phase error. the pll will then begin the normal locking procedure. using refalign with an 8 khz reference if the ZL30410 is locked to an 8 khz re ference, then the ou tput clocks can be brought into phase alignment with the pll reference by using the refalign control pin according to the following procedure: - wait until the ZL30410 lock indication is high, indicating that it is locked - pull refalign low - hold refalign low for 3 sec - pull refalign high after initiating a reference realignment the pll will enter holdover mode for 200ns while aligning the internal clocks to remove static phase error. the pll will then begin the normal locking procedure. 2.3 clock synthesizer the output of th e core pll is connected to the clock synthesizer that generates twelve clocks and three frame pulses. 2.3.1 output clocks the ZL30410 provides the fo llowing clocks (see figure 15 "st-bus an d gci output timing", figure 16 "ds1 and ds2 clock timing", figure 17 "c155o and c19o timing", and figure 20 "e3 and ds3 output timing" for details): - c1.5o : 1.544 mhz clock wi th nominal 50% duty cycle - c2o : 2.048 mhz clock with nominal 50% duty cycle - c4o : 4.096 mhz clock with nominal 50% duty cycle - c6o : 6.312 mhz clock wi th nominal 50% duty cycle - c8o : 8.192 mhz clock wi th nominal 50% duty cycle - c8.5o : 8.592 mhz clock with duty cycle from 30 to 70%. - c11o : 11.184 mhz clock with duty cycle from 30 to 70%. - c16o : 16.384 mhz clock with nominal 50% duty cycle - c19o : 19.44 mhz clock wi th nominal 50% duty cycle - c34o : 34.368 mhz clock with nominal 50% duty cycle - c44o : 44.736 mhz clock with nominal 50% duty cycle
ZL30410 data sheet 11 zarlink semiconductor inc. - c155 : 155.52 mhz clock with nominal 50% duty cycle. the ZL30410 provides the following frame pulses (see figure 15 "st-bus and gci output timing" for details). all frame pulses have the same 125s period (8khz frequency): - f0o : 244 ns wide, logic low frame pulse - f8o : 122 ns wide, logic high frame pulse - f16o : 61 ns wide, logic low frame pulse the combination of two pins, e3ds3/oc3 and e3/ds3, controls the selection of different clock configurations. when the e3ds3/oc3 pin is high then the c155o (155.52 mhz) clock is disabled and the c34/44 clock is output at its nominal frequency. the logic level on the e3/ds3 input determines if the output clock on the c34/44 output is 34.368 mhz (e3) or 44.736 mhz (ds3) (see figure 4, ?c34/c44, c155o clock generation options,? on page 11 for details). figure 4 - c34/c44, c155o clock generation options all clocks and frame pulses (except th e c155) are output with cmos logic levels. the c1 55 clock (155.52 mhz) is output in a standard lvds format. 2.4 control state machine 2.4.1 clock modes the ZL30410 supports three clock modes: free-run, normal (locked) and holdover. all clock modes are defined in the international standards e.g.: g.813, gr-1244- core and gr-253-core and they are supported by a corresponding state in the ZL30410 control state machine. 2.4.2 ZL30410 state machine the ZL30410 control state machine is a combination of many internal states supporting the three mandatory clock modes: free-run, normal and holdover. a simplified state machine diagram that is shown in figure 5 includes these three states which are complemented by two a dditional states: reset and auto holdover. these two additional states are critical to the ZL30410 operation under changing external conditions. c155 output c34/44 output e3ds3/oc3 e3ds3/oc3 0 01 1 155.52 active disabled 11.184 44.736 8.592 34.368 e3/ds3 0 1
ZL30410 data sheet 12 zarlink semiconductor inc. figure 5 - ZL30410 state machine reset state the reset state must be entered when ZL30410 is powered-up . in this state, all arithmetic calculations are halted, and clocks are stopp ed. the reset state is en tered by pulling the reset pin low for a minimum of 1s. when the reset pin is pulled back high, internal logic starts a 625s initialization process before switching into the free-run state (ms2, ms1 = 10). free-run state (free-run mode) the free-run state is entered when synchronization to a network reference is not possible or is not required. typically this occurs during installation or maintenance. in the free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30410 master crystal oscillator. normal state (normal mode or locked mode) the normal state is entered when a good quality reference clock from the network is available for synchronization. the ZL30410 automatically detects the frequency of the re ference clock (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) and sets the lock status pin high after acquiri ng synchronization. in the normal state all generated clocks (c1.5o, c2o, c4o , c6o, c8o, c16o , c19o, c34/c44 and c155) and frame pulses (f0o , f8o, f16o ) are synchronized to the master timing card. to guarantee uninterrupted synchronization, the ZL30410 has two acquisition plls that continuously monitor the qualit y of the incoming reference cl ocks. this dual architecture enables quick replacement of a poor or failed reference and minimizes the time spent in other states. state ms2,ms1 notes: --> - external transition {auto} - automatic internal transition {manual} - user initiated transition ref: ok and ms2,ms1=00 {auto} ref: ok-->fail and ms2,ms1=00 {auto} ms2,ms1=01 or refsel change ms2,ms1=10 forces unconditional return from any state to free-run reset =1 ms2,ms1=00 or ms2,ms1=01 refsel change or ms2,ms1=01 ref: fail-->ok and ms2,ms1=00 {auto} reset free- run 10 hold- over 01 normal 00 auto hold- over
ZL30410 data sheet 13 zarlink semiconductor inc. holdover state (holdover mode) the holdover state is typically entered for a short dura tion while synchronization with the network is temporarily disrupted. in holdover mode, the zl3041 0 generates clocks, which are not locked to an ex ternal reference signal but their frequencies are based on stored coefficients in memory that were determined while the pll was in normal mode and locked to an external reference signal. the initial frequency offset of the ZL30410 in holdover mode is 70x10 -12 . this is more accurate than telcordia?s gr-1244-core stratum 3e requirement of + 1x10 -9 . when the ZL30410 is transitioned into holdover mode, holdover stability is determined by the stability of the 20 mhz master clock oscillator. selection of the oscillator requires close examination of the crystal oscillator temp erature sensitivity and freque ncy drift caused by aging. auto holdover state the auto holdover state is a transitional state that th e ZL30410 enters automatically when the active reference fails unexpectedly. when the ZL30410 detects loss of reference it sets the holdover status pin and waits in auto holdover state until the failed reference recovers. recovery from auto holdover for 8 khz, 1.544 mhz, 2.048 mhz and 19.44 mhz reference clocks is fu lly automatic, however recovery fo r an 8 khz reference clock requires additional transitioning through the holdover state to guarantee compliance with network synchronization standards (for details see section 4.1.3 on pa ge 18 and section 4.1.2 on page 17). the holdover status may alert the external control processor (or cpld logic) about the failur e and in response the control processor may switch to the secondary reference clock. the auto holdover and holdover states are internally combined together and they are output as a holdover status on pin 55. 2.4.3 state transitions in a typical application, the ZL30410 will most of the time operate in normal mode (ms2, ms1 == 00) generating synchronous clocks. its two acquisition plls will continuou sly monitor the input references for signs of degraded quality and output status information for further processi ng. the status information from the acquisition plls and the core pll combined with status information from line interfaces and framers (as listed below) forms the basis for creating reliable network synchronization. - acquisition plls (prior, secor) - core pll (lock, holdover) - line interfaces (e.g. los - loss of signal, ais - alarm indication signal) - framers (e.g. lof - loss of frame or synchronization status messages carried over sonet s1 byte or esf-ds1 facility data link). the ZL30410 state machine is designed to perform some transitions automatically, leaving other less time dependent tasks to the extern al controlling processor (o r cpld logic). the state ma chine includes two stimulus signals which are critical to automatic operation: ?ok --> fail? and ?fail --> ok? that represent loss (and recovery) of reference signal or its drift by more than 30000 ppm. both of them force the core pll to transition into and out of the auto holdover state. the ZL30410 state machine is driven by controlling the mode select pins ms2, ms1 and refsel. in order to avoid synchronization problems, the st ate machine has built-in basic protection that does not allow switching the core pll into a state where it cannot operate correctly e.g. it is not possible to force the core pll into normal mode when all references are lost.
ZL30410 data sheet 14 zarlink semiconductor inc. 2.5 jtag interface the ZL30410 jtag (joint test action group) interface conforms to the boundary-scan sta ndard ieee114 9.1-1990, which specifies a design-for-testability technique called boundary-scan test (bst). the bst architecture is made up of four basic elements, test access port (tap), tap cont roller, instruction register (ir) and test data registers (tdr) and all these elements are implemented on the ZL30410. zarlink semiconductor provides a boundary scan descr iption language (bsdl) file that contains all the information required for a jt ag test system to a ccess the ZL30410's boundary scan circ uitry. the file is available for download from the zarlink semiconductor web site: www.zarlink.com. 3.0 control interface the ZL30410 has a built-in simple control interface that makes it suitable for application that can provide only a limited amount of supervision. this allows for building mu lti-service line cards without extensive programming. the complete set of control and status pins is sh own in figure 6 - control interface on page 14. figure 6 - control interface 3.1 control pins the ZL30410 has five dedicated control pins for selecting modes of operation and activating different functions. these pins are listed below: ms2 and ms1 pins : mode select : the ms2 (pin 19) and ms1 (pin 18) inputs select the pll mode of operation. see table 1 for details. the logic level at these inputs is sampled by the rising edge of the f8o frame pulse. ms2 ms1 mode of operation 0 0 normal mode 0 1 holdover mode 10free-run 11reserved table 1 - operating modes and states c o n t r o l s t a t u s input pins lock holdover prior secor ms2 ms1 fcs refsel refalign output pins
ZL30410 data sheet 15 zarlink semiconductor inc. fcs pin : filter characteristic select . the fcs (pin 9) input is used to select the filtering characteristics of the core pll. see table 2 on page 15 for details. refsel : reference source select . the refsel (pin 47) input selects the pri (primary) or sec (secondary) input as the reference clock for the core pll. the logic level at this input is sampled by the rising edge of f8o. refalign : reference alignment . the refalign (pin 48) input controls phase realignment between the input reference and the generated output clocks. see section 2.2.4 on page 9 for details. 3.2 status pins the ZL30410 has four dedicated status pins for indicati ng modes of operation and quality of the primary and secondary reference clocks. th ese pins are listed below: lock . this output goes high after the ZL30410 has complete d its locking sequence (see section 2.2.3 for details). holdover - this output goes high when the core pll enters holdover mode. the core pll will switch to holdover mode if the respective acquisition pll enters holdover mode or if the mode select pins are set to holdover (ms2, ms1 = 01). prior - (primary reference out of range). the prior status is based on two detectors that monitor reference quality with different precision and response times. outputs of both detectors are combined together (or function) to drive prior status pin. this output goes high when one of the detectors is triggered by the failing primary reference clock: - slow response detector (high precision): this detecto r detects if the primary reference is off its nominal frequency by more than 12 ppm. the frequency offset monitor updates internally every 10 sec and will change state after two matching measurements (pass/pass or fail/fail). this is in full compliance with the gr-1244-core requirement of 10 to 30 sec reference validation time. this output returns to zero when the reference frequency is requalified within 9.2 ppm of the nominal frequency (monitor circuit has built-in hysteresis). in an extreme case, when over time the master clock oscillator drifts 4.6 ppm the switching thresholds will change as well, as is shown in figure 7. - fast response detector (low precision): this detector detects a large frequency offset (greater than 3%) or large change in a single cycle period (grate r than 30%). in both case s detector will almost instantaneously (in less than 250s) disqualify the reference and reset the 10 sec internal timer. fcs filtering characteristic phase slope limit 0 filter corner frequency set to 12hz. this selection meets loop filter characteristics for line card applications n/a 1 filter corner frequency set to 6hz. this selection meets requirements of g.813 option 1 41 ns in 1.326 ms table 2 - filter characteristic selection refsel input reference 0 core pll connected to t he primary acquisition pll 1 core pll connected to the secondary acquisition pll table 3 - reference source select
ZL30410 data sheet 16 zarlink semiconductor inc. secor - (secondary reference out of range). functionally, this pin is equivalent to the prior pin for primary acquisition pll. figure 7 - primary and secondary reference out of range thresholds 4.0 applications this section provides application exam ples frequently found in a typical line card being part of network element operating in a synchronous network. 4.1 ZL30410 switching between clock modes the ZL30410 is designed to transition from one mode to the other driven by the in ternal state machine or by external control. the following examples present a co uple of typical scenarios of how the ZL30410 can be employed in network interface line cards. 4.1.1 system start-up sequence: free-run --> holdover --> normal the free-run to holdover to normal transition represents a sequence of steps that will most likely occur during a new system installa tion or scheduled ma intenance. the process starts from the reset state and then transitions to free-run mode where the system (card) is being initialized. at the end of this process the ZL30410 should be switched into norma l mode (with ms2, ms1 set to 00) instead of holdover mode. if the reference clock is available, the ZL30410 will transition briefly into holdov er to acquire synchronization and switch automatically to normal mode. if the reference clock is not available at this time, as it ma y happen during new system installation, then the ZL30410 will stay in holdover indefinitely. while in holdover mode, the core pll will continue generating clocks with the same accuracy as in the free-run mode, waiting for a go od reference clock. when the line card become connected to the timing card the acquisition pll will quickly synchronize and clear its own holdover status. this will enable the core pll to start the synchroni zation process. after acquiring lock, the ZL30410 will automatically switch from holdover in to normal mode with out system intervention. this transition to the normal mode will be flagged by the lock status pin. c20i clock 0 ppm +4.6 ppm -4.6 ppm accuracy -9.2 0 7.4 12 -12 9.2 c20 c20 -7.4 -4.6 4.6 13.8 16.6 4.6 -4.6 -16.6 -13.8 -15 -10 0 -20 -5 5 10 15 20 frequency out of range out of range out of range in range in range in range offset [ppm] 0 0 c20
ZL30410 data sheet 17 zarlink semiconductor inc. figure 8 - transition from free-run to normal mode 4.1.2 single reference operation: normal --> auto holdover --> normal the normal to auto-holdover to normal transition will usually happen when the line card loses its single reference clock unexpectedly. the sequence starts with the reference clock transitioning from ok --> fail at a time when ZL30410 operates in normal mode (as is shown in figure 10). this failure is detected by the active acquisition pll based on the following fail criteria: - frequency offset on 8 khz, 1. 544 mhz, 2.048 mhz a nd 19.44 mhz reference clocks exceeds 30000 ppm (3%). - single phase hit on 1.544 mhz, 2.048 mhz and 19.44 mh z exceeds half of the cycle of the reference clock. after detecting any of these anomalies on a reference clock the acquisition pll will switch itself into holdover mode forcing the core pll to automatically s witch into the auto holdover state. th is condition is flagged by lock = 0 and holdover = 1. figure 9 - automatic entry into auto holdover state and recovery into normal mode ref: ok and ms2,ms1=00 {auto} ref: ok-->fail and ms2,ms1=00 {auto} ms2,ms1=01 or refsel change ms2,ms1=10 forces unconditional return from any state to free-run reset =1 ms2,ms1=00 or ms2,ms1=01 refsel change or ms2,ms1=01 ref: fail-->ok and ms2,ms1=00 {auto} reset free- run 10 hold- over 01 normal 00 auto hold- over ref: ok and ms2,ms1=00 {auto} ref: ok-->fail and ms2,ms1=00 {auto} ms2,ms1=01 or refsel change ms2,ms1=10 forces unconditional return from any state to free-run reset =1 ms2,ms1=00 or ms2,ms1=01 refsel change or ms2,ms1=01 ref: fail-->ok and ms2,ms1=00 {auto} reset free- run 10 hold- over 01 normal 00 auto hold- over
ZL30410 data sheet 18 zarlink semiconductor inc. the core pll will automatically return to the normal stat e after the reference signal recovers from failure. this transition is shown on the state diagram as a fail --> ok change. this change becomes effective when the reference is restored and there have been no phase hits detect ed for at least 64 clock cycles for the 1.544/2.048 mhz reference, 512 clock cycles for the 19.44 mhz reference and 1 clock cycle for the 8 khz reference. this transition from auto holdover to normal mode is per formed as ?hit-less? recovery for 1.544 mhz, 2.048 mhz and 19.44 mhz references. for the 8 khz input reference, the recovery from auto holdover state must transition through the holdover state to guarantee ?hit-less? re covery (for details see section 4.1.3 on page 18). 4.1.3 single 8 khz reference operation: normal --> auto holdover--> holdover --> normal the sequence starts from the normal state and transitions to auto holdover state due to an unforeseen loss of the 8 khz reference. the failure conditions triggering this transition are described in sect ion 4.1.2. when in the auto holdover state, the ZL30410 can return to normal mode autom atically but this transition may exceed output phase continuity limits specified in the performance characteristic table listed in section ?performance characteristics? on page 29. this probable time interval error is avoidable by forcing the pll into holdover state immediately after detection of the 8 khz reference failure. while in holdover state the ZL30410 will continue monitoring quality of the input reference (if a proper 4.6ppm master clock oscillator is employed) and after detecting the presence of a valid reference it can be switched into normal state. when t he master clock oscillator a ccuracy exceeds 4.6ppm range (leading to inaccurate internal out-of-range detection) then an external method for detecting the presence of the clock should be employed to switch the ZL30410 into normal state (0.1 sec after detecting the presence of a valid 8 khz reference). figure 10 - recovery procedure from a single 8 khz reference failure by transitioning through the holdover state ref: ok and ms2,ms1=00 {auto} ref: ok-->fail and ms2,ms1=00 {auto} ms2,ms1=01 or refsel change ms2,ms1=10 forces unconditional return from any state to free-run reset =1 ms2,ms1=00 or ms2,ms1=01 then set ms2,ms1=01 ref: fail-->ok and ms2,ms1=00 {auto} reset free- run 10 hold- over 01 normal 00 auto hold- over when holdover 0-->1
ZL30410 data sheet 19 zarlink semiconductor inc. 4.1.4 dual reference operation: normal --> auto holdover--> holdover --> normal the normal to auto-holdover to holdover to normal sequence represents the most likely operation of the ZL30410. the sequence starts from the normal state and transition s to auto holdover state due to an unforeseen loss of reference. the failure conditions triggering this transi tion were described in section 4.1.2. when in the auto holdover state, the ZL30410 can return to normal mode automatically if the lost reference is restored. this transition from auto holdover to normal mode is performe d as ?hit-less? recovery for 1.544 mhz, 2.048 mhz and 19.44 mhz references. for the 8 khz input reference, the recovery from auto holdover state must transition through the holdover state to guarantee ?hit-less? recove ry (for details see section 4.1.3 on page 18). if the reference clock failure persi sts for a period of time that exceeds the system desi gn limit, the system control processor may initiate a reference switch. if the secondar y reference is available the ZL30410 will briefly switch into holdover mode and then transition to normal mode. figure 11 - entry into auto holdover state and recovery into normal mode by switching references the new reference clock will most likely have a different p hase but it may also have a different fractional frequency offset. in order to lock to a new reference with a different frequency, the core pll may be stepped gradually towards the new frequency. ref: ok and ms2,ms1=00 {auto} ref: ok-->fail and ms2,ms1=00 {auto} ms2,ms1=01 or refsel change ms2,ms1=10 forces unconditional return from any state to free-run reset =1 ms2,ms1=00 or ms2,ms1=01 refsel change or ms2,ms1=01 ref: fail-->ok and ms2,ms1=00 {auto} reset free- run 10 hold- over 01 normal 00 auto hold- over
ZL30410 data sheet 20 zarlink semiconductor inc. 4.1.5 reference switching (refse l): normal --> holdover --> normal the normal to holdover to normal mode switching is usually performed when: - a reference clock is available but its frequency drif ts beyond some specified limit. in a network element with stratum 3 internal cl ocks, the reference failure is declared when its frequency drifts more than 12ppm beyond its nominal frequency. the ZL30410 indicates this condition by setting prior or secor status pins to logic high. - during routine maintenance of equipment when orderly switching of reference clocks is possible. this may happen when synchronization references must be rearranged or when a faulty timing card must be replaced. figure 12 - manual reference switching two types of transitions are possible: - semi-automatic transition, which involves changing refsel input to select a secondary reference clock without changing the mode select inputs ms2,ms1=00 (normal mode). this forces the ZL30410 to momentarily transition through the holdover stat e and automatically return to normal mode after synchronizing to a secondary reference clock. - manual transition, which involves switching into holdover mode (ms2,ms1=01), changing references with refsel, and manual return to the normal mode (ms2, ms1=00). in both cases, the change of references provides ?hit-less? switching. ref: ok and ms2,ms1=00 {auto} ref: ok-->fail and ms2,ms1=00 {auto} ms2,ms1=01 or refsel change ms2,ms1=10 forces unconditional return from any state to free-run reset =1 ms2,ms1=00 or ms2,ms1=01 refsel change or ms2,ms1=01 ref: fail-->ok and ms2,ms1=00 {auto} reset free- run 10 hold- over 01 normal 00 auto hold- over
ZL30410 data sheet 21 zarlink semiconductor inc. 4.2 power supply filtering figure 13 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. figure 13 - power supply filtering ZL30410 40 42 44 46 48 50 52 54 56 58 60 22 24 26 28 30 34 36 38 32 62 80 78 76 74 72 68 66 64 70 20 18 16 14 12 10 8 6 4 2 gnd vdd avdd gnd gnd gnd vdd gnd gnd vdd vdd gnd vdd gnd vdd gnd c2 c5 c4 c3 c6 c7 fb c1 c1, c2, c3, c4, c5 = 0.1 f (ceramic) c6, c7 = 1 f (ceramic) fb - ferrite bead = blm21a601r (murrata)
ZL30410 data sheet 22 zarlink semiconductor inc. 5.0 characteristics 5.1 ac and dc electrical characteristics * voltages are with respect to ground (gnd) unless otherwise stated * exceeding these values may cause permanent damage. fu nctional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated * voltages are with respect to ground (gnd) unless otherwise stated note 1: vos is defined as (v oh + v ol ) / 2 note 2: rise and fall times are measured at 20% and 80% levels. absolute maximum ratings* parameter symbol min max units 1 supply voltage v ddr -0.3 7.0 v 2 voltage on any pin v pin -0.3 vdd+0.3 v 3 current on any pin i pin 30 ma 4 storage temperature t st -55 125 c 5 package power dissipation (80 pin lqfp) p pd 1000 mw 6 esd rating v esd 1500 v recommended operating conditions * characteristics symbol min typ max units 1 supply voltage v dd 3.0 3.3 3.6 v 2 operating temperature t a -40 25 +85 c dc electrical characteristics* characteristics symbol min max units notes 1 supply current with c20i = 20mhz i dd 155 ma outputs unloaded 2 supply current with c20i = 0v i dds 3.5 ma outputs unloaded 3 cmos high-level input voltage v cih 0.7v dd v 4 cmos low-level input voltage v cil 0.3v dd v 5 input leakage current i il 15 av i =v dd or gnd 6 high-level output voltage v oh 2.4 v i oh =10ma 7 low-level output voltage v ol 0.4 v i ol =10ma 8 lvds: differential output voltage v od 250 450 mv z t =100 ? 9 lvds: change in vod between complementary output states dv od 50 mv z t =100 ? 10 lvds: offset voltage v os 1.125 1.375 v note 1 11 lvds: change in vos between complementary output states dv os 50 mv 12 lvds: output short circuit current i os 24 ma pin short to gnd 13 lvds: output rise and fall times t rf 260 900 ps note 2
ZL30410 data sheet 23 zarlink semiconductor inc. * voltages are with respect to ground (gnd) unless otherwise stated * supply voltage and operating temperature are as per recommended operating conditions * timing for input and output signals is based on the worst case conditions (over t a and v dd ) figure 14 - timing parameters measurement voltage levels ac electrical characteristics - timing parameter measurement - cmos voltage levels * characteristics symbol level units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v all signals timing reference points v hm v t v lm t if, t of t ir, t or
ZL30410 data sheet 24 zarlink semiconductor inc. - * supply voltage and operating temperature are as per recommended operating conditions figure 15 - st-bus and gci output timing ac electrical characteristics - st-bus and gci output timing* characteristics symbol min max units notes 1 f16o pulse width low (nom 61 ns) t f16l 56 62 ns 2 f8o to f16o delay t f16d 27 33 ns 3 c16o pulse width low t c16l 26 32 ns 4 f8o to c16o delay t c16d -3 3 ns 5 f8o pulse width high (nom 122 ns) t f8h 119 125 ns 6 c8o pulse width low t c8l 56 62 ns 7 f8o to c8o delay t c8d -3 3 ns 8 f0o pulse width low (nom 244 ns) t f0l 241 247 ns 9 f8o to f0o delay t f0d 119 125 ns 10 c4o pulse width low t c4l 119 125 ns 11 f8o to c4o delay t c4d -3 3 ns 12 c2o pulse width low t c2l 240 246 ns 13 f8o to c2o delay t c2d -3 3 ns t f16l t f16d t c16d v t tc =125 s tc = 61.04 ns t f8h t c8l t c8d t f0l t f0d tc =125 s tc = 122.07 ns tc =125 s tc = 244.14 ns tc = 488.28 ns t c4l t c4d t c2d t c2l f16o f8o c16o c8o f0o c4o c2o t c16l v t v t v t v t v t v t
ZL30410 data sheet 25 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 16 - ds1 and ds2 clock timing ac electrical characteristics - ds1 and ds2 clock timing* characteristics symbol min max units notes 1 c6o pulse width low t c6l 75 83 ns 2 f8o to c6o delay t c6d -4 11 ns 3 c1.5o pulse width low t c1.5l 320 328 ns 4 f8o to c1.5o delay t c1.5d -4 11 ns f8o c6o c1 . 5o tc =125 s tc = 158.43 ns t c6d v t v t v t t c1.5l t c6l tc = 647.67 ns t c1.5d
ZL30410 data sheet 26 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 17 - c155o and c19o timing ac electrical characteristics - c155o and c19o clock timing characteristics symbol min max units notes 1 c155o pulse width low t c155l 2.6 3.8 ns 2 c155o to c19o rising edge delay t c19dlh -1 7 ns 3 c155o to c19o falling edge delay t c19dhl -2 6 ns 4 c19 pulse width high t c19h 23 29 t c155l t c19dlh t c19dhl 1.25v v t tc = 6.43 ns tc = 51.44 ns note: delay is measured from the rising edge of c155p clock (single ended) at 1.25v threshold to the rising and falling edges of c19o clock at v t threshold c155op c19o t c19h
ZL30410 data sheet 27 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 18 - input reference to output clock phase alignment ac electrical characteristics - input to output phase offs et (after phase realignment) * characteristics symbol min max units notes 1 8 khz ref pulse width high or low t r8w 100 ns 2 8 khz ref input to f8o delay t r8d 13 31 ns 3 1.544 mhz ref: pulse width high or low t r1.5w 100 ns 4 1.544 mhz ref input to f8o delay t r1.5d 335 350 ns 5 2.048 mhz ref: pulse width high or low t r2w 100 ns 6 2.048 mhz ref input to f8o delay t r2d 255 272 ns 7 19.44 mhz ref: pulse width high or low t r19w 20 ns 8 19.44 mhz ref input to f8o delay t r19d 821ns 9 f8o to c19o delay t c19d -5 7 ns 10 reference input rise and fall time t ir , t if 10 ns t r8d t r1.5d t r2d t r19d t r8w t r1.5w t r2w t r19w tc = 125 s tc = 647.67 ns tc = 488.28 ns tc = 51.44 ns tc = 51.44 ns tc = 125 s pri/sec 8 khz pri/sec 1.544 mhz pri/sec 2.048 mhz pri/sec 19.44 mhz c19o f8o v t v t v t v t v t v t note: delay time measurements are done with jitter free input reference signals t c19d
ZL30410 data sheet 28 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 19 - input control signal setup and hold time * supply voltage and operating temperature are as per recommended operating conditions figure 20 - e3 and ds3 output timing ac electrical characteristi cs - input control signals * characteristics symbol min max units notes 1 input controls setup time t s 100 ns 2 input controls hold time t h 100 ns ac electrical characteristics - e3 and ds3 output timing* characteristics symbol min max units notes 1 c44o clock pulse width high t c44h 11 13 ns 2 c11o clock pulse width high t c11h 526ns 3 c34o clock pulse width high t c34h 13 16 ns 4 c8.5o clock pulse width high t c8.5h 924ns t s v t v t t h f8o ms1, ms2 refsel, fcs, refalign e3/ds3 e3ds3/oc3 t c44h v t t c34h t c8.5h c44o tc = 22.35 ns tc = 89.41 ns tc = 29.10 ns tc = 116.39 ns c11o c34o c8.5o v t v t v t t c11h
ZL30410 data sheet 29 zarlink semiconductor inc. 5.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions performance characteristics* characteristics min typ max units notes 1 holdover accuracy (6hz filter) 70x10 -12 160x10 -12 hz/hz 2 holdover accuracy (12hz filter) 140x10 -12 320x10 -12 hz/hz 3 holdover stability na hz/hz holdover stability is determined by stability of the 20 mhz master clock oscillator 4 capture range -104 +104 ppm the 20 mhz master clock oscillator set at 0ppm 5 reference out of range threshold -12 +12 ppm the 20 mhz master clock oscillator set at 0ppm lock time 6 6 hz or 12 hz filter 6 s 4.6ppm frequency offset 7 6 hz or 12 hz filter 6 s 20ppm frequency offset output phase continuity (mtie) 8 reference switching: pri ? sec, sec ? pri 50 5 ns ns pri = sec = 8 khz pri or sec = 1.544 mhz, 2.048 mhz, 19.44 mhz 9 switching from normal mode to holdover mode 0ns 10 switching from holdover mode to normal mode 50 2 ns ns pri = sec = 8 khz pri or sec = 1.544 mhz, 2.048 mhz, 19.44 mhz output phase slope 11 6 hz loop filter 41 ns 1.326ms
ZL30410 data sheet 30 zarlink semiconductor inc. performance characteristics : measured output jitter - gr-253 -core and t1.105.03 conformance * supply voltage and operating temperature are as per recommended operating conditions performance characteristics : measured output jitter - t1.403 conformance * supply voltage and operating temperature are as per recommended operating conditions telcordia gr-253-core and ansi t1.105.03 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c155 clock output 1oc-3 155.52 mbit/s 65khz to 1.3mhz 0.15 uipp 0.964 0.325 ns p-p 2 12khz to1.3mhz (category ii) 0.1 uipp 0.643 0.408 ns p-p 0.01 ui rms 0.064 0.038 ns rms 3 500hz to 1.3mhz 1.5 uipp 9.645 0.448 ns p-p c19 clock output 4oc-3 155.52 mbit/s 65khz to 1.3mhz 0.15 uipp 0.964 0.390 ns p-p 5 12khz to1.3mhz (category ii) 0.1 uipp 0.643 0.458 ns p-p 0.01 ui rms 0.064 0.040 ns rms 6 500hz to 1.3mhz 1.5 uipp 9.645 0.512 ns p-p ansi t1.403 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c1.5 clock output 1ds1 1.544 mbit/s 8 khz to 40 khz 0.07 uipp 45.3 0.63 ns p-p 2 10 hz to 40 khz 0.5 uipp 324 0.93 ns p-p
ZL30410 data sheet 31 zarlink semiconductor inc. performance characteristics : measured output jitter - g. 7 4 7 conformance * supply voltage and operating temperature are as per recommended operating conditions performance characteristics : measured output jitter - t1.404 conformance * supply voltage and operating temperature are as per recommended operating conditions itu-t g.747 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c6 clock output 1ds2 6312 kbit/s 10 hz to 60khz 0.05 uipp 7.92 0.53 ns p-p ansi t1.403 jitter generation requirements ZL30410 jitter generation performance interface type i jitter measurement filter limit in ui equivalent limit in time domain typ units notes c44 clock output 1ds3 44.736 mbit/s 30 khz to 400 khz 0.05 uipp 1.12 0.30 ns p-p 2 10 hz to 400 khz 0.5 uipp 11.2 0.47 ns p-p
ZL30410 data sheet 32 zarlink semiconductor inc. performance characteristics : measured output jitter - g.732, g.735 to g.739 conformance * supply voltage and operating temperature are as per recommended operating conditions performance characteristics : measured output jitter - g. 7 5 1 conformance * supply voltage and operating temperature are as per recommended operating conditions itu-t g.732, g.735, g.736, g.737, g.738, g.739 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c16 , c8, c4 and c2 clock outputs 1e1 2048 kbit/s 20 hz to 100 khz 0.05 uipp 24.4 0.56 ns p-p itu-t g.751 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c34 clock output 1e3 34368 kbit/s 100 hz to 800 khz 0.05 uipp 1.45 0.64 ns p-p
ZL30410 data sheet 33 zarlink semiconductor inc. performance characteristics : measured output jitter - g. 8 1 2 conformance * supply voltage and operating temperature are as per recommended operating conditions itu-t g.812 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c155 clock output 1 stm-1 optical 155.52 mbit/s 65khz to 1.3mhz 0.1 uipp 0.643 0.325 ns p-p 2 500hz to 1.3mhz 0.5 uipp 3.215 0.448 ns p-p c155 clock output 3 stm-1 electrical 155.52 mbit/s 65khz to 1.3mhz 0.075 uipp 0.482 0.325 ns p-p 4 500hz to 1.3mhz 0.5 uipp 3.215 0.448 ns p-p c19 clock output 5 stm-1 optical 155.52 mbit/s 65khz to 1.3mhz 0.1 uipp 0.643 0.390 ns p-p 6 500hz to 1.3mhz 0.5 uipp 3.215 0.512 ns p-p c19 clock output 7 stm-1 electrical 155.52 mbit/s 65khz to 1.3mhz 0.075 uipp 0.482 0.390 ns p-p 8 500hz to 1.3mhz 0.5 uipp 3.215 0.512 ns p-p c16 , c8, c4 and c2 clock outputs 9e1 2048 kbit/s 20 hz to 100 khz 0.05 uipp 24.4 0.56 ns p-p c1.5 clock output 10 ds1 1.544 mbit/s 10 hz to 40 khz 0.05 uipp 32.4 0.93 ns p-p
ZL30410 data sheet 34 zarlink semiconductor inc. performance characteristics : measured output jitter - g. 8 1 3 conformance (option 1) * supply voltage and operating temperature are as per recommended operating conditions itu-t g.813 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes option 1 c155 clock output 1 stm-1 155.52 mbit/s 65khz to 1.3mhz 0.1 uipp 0.643 0.325 ns p-p 2 500hz to 1.3mhz 0.5 uipp 3.215 0.448 ns p-p c19 clock output 3 stm-1 155.52 mbit/s 65khz to 1.3mhz 0.1 uipp 0.643 0.390 ns p-p 4 500hz to 1.3mhz 0.5 uipp 3.215 0.512 ns p-p c16 , c8, c4 and c2 clock outputs 5e1 2048 kbit/s 20 hz to 100 khz 0.05 uipp 24.4 0.56 ns p-p
ZL30410 data sheet 35 zarlink semiconductor inc. performance characteristics : measured output jitter - en 300 462-7-1 conformance * supply voltage and operating temperature are as per recommended operating conditions etsi en 300 462-7-1 jitter generation requirements ZL30410 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c155 clock output 1 stm-1 optical 155.52 mbit/s 65khz to 1.3mhz 0.1 uipp 0.643 0.325 ns p-p 2 500hz to 1.3mhz 0.5 uipp 3.215 0.448 ns p-p c155 clock output 3 stm-1 electrical 155.52 mbit/s 65khz to 1.3mhz 0.075 uipp 0.482 0.325 ns p-p 4 500hz to 1.3mhz 0.5 uipp 3.215 0.448 ns p-p c19 clock output 5 stm-1 optical 155.52 mbit/s 65khz to 1.3mhz 0.1 uipp 0.643 0.390 ns p-p 6 500hz to 1.3mhz 0.5 uipp 3.215 0.512 ns p-p c19 clock output 7 stm-1 electrical 155.52 mbit/s 65khz to 1.3mhz 0.075 uipp 0.482 0.390 ns p-p 8 500hz to 1.3mhz 0.5 uipp 3.215 0.512 ns p-p
ZL30410 data sheet 36 zarlink semiconductor inc. performance characteristics - measured output jitter - unfiltered * characteristics typ (ul pp ) typ ( ns pp ) notes 1 c1.5o (1.544mhz) 0.0042 2.71 2 c2o (2.048mhz) 0.0019 0.95 3 c4o (4.096mhz) 0.0037 0.92 4 c6o (6.312mhz) 0.0179 2.84 5 c8o (8.192mhz) 0.0081 0.99 6 c8.5o (8.592mhz) 0.0222 2.58 7 c11o (11.184mhz) 0.0295 2.64 8 c16o (16.384mhz) 0.0161 0.98 9 c19o (19.44mhz) 0.0125 0.64 10 c34o (34.368mhz) 0.0433 1.26 11 c44o (44.736mhz) 0.0546 1.22 12 c155o (155.52mhz) 0.0867 0.56 13 f0o (8khz) na 0.44 14 f8o (8khz) na 0.46 15 f16o (8khz) na 0.45

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